Internal voltage generation circuit of semiconductor memory device

ABSTRACT

Disclosed herein is an internal voltage generation circuit of a semiconductor memory device which is capable of supplying voltages of different levels to a column path &amp; control logic and data path &amp; control logic in the memory device according to different operation modes of the memory device. The column path &amp; control logic and data path &amp; control logic are applied with a normal operating voltage when they are involved in the current operation mode of the memory device, whereas with a lower voltage when they are not involved. Therefore, the present invention has the effect of efficiently managing internal voltages of the semiconductor memory device and reducing current leakage of the memory device and, in turn, unnecessary power consumption thereof.

This application relies for priority upon Korean Patent Application No.2004-0025060 filed on Apr. 12, 2004, the contents of which are hereinincorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an internal voltage generation circuitof a semiconductor memory device, and more particularly to an internalvoltage generation circuit for supplying voltages of different levels toa specific area in a semiconductor memory device according to whetherthe specific area is involved in the current operation mode of thememory device, so as to reduce current leakage and power consumption ofthe memory device.

2. Description of the Related Art

FIG. 1 is a general conceptual diagram of a semiconductor memory device.As shown in this drawing, the semiconductor memory device basicallycomprises a cell array, a row path & control logic 11, a column path &control logic 15, and a data path & control logic 14. Among these, therow path & control logic 11, the column path & control logic 15 and thedata path & control logic 14 are typically called a peri area in thegross.

FIG. 2 is a conceptual diagram of an internal voltage generation circuitof a conventional semiconductor memory device. As shown in this drawing,if an external voltage Vcc is applied to the memory device, theninternal voltages necessary for the operation of the memory device areinternally generated in the memory device. These internal voltages maybe, for example, a high voltage Vpp to a word line, a voltage Vcore to acell and bit line sense amplifier, a high voltage source Vperi to a periarea, etc.

In the conventional memory device, once the internally generated voltageVperi is determined in level, it is applied in common to all componentsin the peri area That is, once being generated, the voltage Vperi of thesame level is applied to all of a row path & control logic, column path& control logic and data path & control logic in the peri area

Recently, in a semiconductor memory device, the external voltage Vcc hasgradually become lower in level as the memory device has become higherin speed and lower in power. As a result, the internal voltages for theinternal operation of the memory device have become lower in level, too,resulting in there being a need to reduce a threshold voltage Vt of atransistor so as to secure the operation margin of the memory device.However, as the threshold voltage has become lower in level, the memorydevice has increased in current leakage and, in turn, in powerconsumption For this reason, there has been a need to reduce the currentleakage resulting from the fact that the external voltage Vcc is lowerin level.

However, in the conventional semiconductor memory device, as mentionedabove, the voltage of the same level is supplied to the entire peri areairrespective of the operation mode of the memory device, thereby makingit impossible to control the voltage level based on the operation modeof the memory device. For this reason, there is no room to reduce powerconsumption of the memory device by preventing unnecessary currentleakage thereof.

In detail, in a semiconductor memory device, when the memory device isin an active mode, all components of a peri area are involved in theactive mode. However, when the memory device is in a standby modeincluding a refresh mode, only a row path & control logic in the periarea is involved in the standby mode, but the other components in theperi ea, or a column path & control logic and a datapath & controllogic, are not involved therein Accordingly, in order to reduceunnecessary current leakage of the memory device, it is required tosupply a voltage of a desired level to only the involved components anda voltage of a lower level to the other components, respectively.However, the conventional semiconductor memory device is designed tosupply the voltage of the same level to the entire peri area regardlessof the operation mode thereof resulting in inevitable occurrence ofunnecessary current leakage as mentioned above.

SUMMARY OF THE INVENTION

Therefore, the present invention has been made in view of the aboveproblems and it is an object of the present invention to provide aninternal voltage generation circuit of a semiconductor memory devicewhich is capable of, according to the current operation mode of thememory device, supplying a voltage of a desired level to components in aperi area, involved in the operation mode, and a voltage of a lowerlevel to the other components in the peri area, not involved in theoperation mode, respectively, thereby reducing current leakage and powerconsumption of the memory device.

In accordance with an aspect of the present invention, the above andother objects can be accomplished by the provision of an internalvoltage generation circuit of a semiconductor memory device comprising:reference voltage generation means for generating a reference voltage asa control signal for internal voltage supply; fast internal voltagegeneration means for generating a first internal voltage of a desiredlevel in response to the reference voltage from the reference voltagegeneration means; and second internal voltage generation meansresponsive to an enable signal resulting from a logical operation of anactive control signal indicative of an active mode and a refresh controlsignal indicative of a refresh mode and the reference voltage from thereference voltage generation means, for generating a second internalvoltage of the same level as that of the first internal voltage when thememory device is in the active mode and a third internal voltage of alevel lower than that of the fist internal voltage when the memorydevice is in any other mode including the refresh mode.

Preferably, the first internal voltage is supplied to a row path &control logic in the memory device and the second and third internalvoltages are supplied to a column path & control logic and a data path &control logic in the memory device.

Preferably, the fist internal voltage generation means includes: currentmirror amplification means for comparing the first internal voltage withthe reference voltage to obtain a difference therebetween and amplifyingthe obtained difference; and pull-up means for raising the level of thefirst internal voltage to that of the reference voltage if it becomeslower than the level of the reference voltage.

Preferably, the second internal voltage generation means includes:current minor amplification means responsive to the enable signal for,only when the memory device is in the active mode, comparing the secondinternal voltage with the reference voltage to obtain a differencetherebetween and amplifying the obtained difference; pull-up means forraising the level of the second internal voltage to that of thereference voltage if it becomes lower than the level of the referencevoltage; and a MOS (Metal-Oxide Semiconductor) diode for generating thethird internal voltage of the level lower than that of the firstinternal voltage at an output terminal of the second internal voltagegeneration means when the memory device is in any other mode includingthe refresh mode.

The first internal voltage generation means may include: first currentmirror amplification means for comparing the first internal voltage withthe reference voltage to obtain a difference therebetween and amplifyingthe obtained difference; and first pull-up means for rising the level ofthe first internal voltage to that of the reference voltage if itbecomes lower than the level of the reference voltage; and the secondinternal voltage generation means may include: second current minoramplification means responsive to the enable signal for, only when thememory device is in the active mode, comparing the second internalvoltage with the reference voltage to obtain a difference therebetweenand amplifying the obtained difference; second pull-up means for raisingthe level of the second internal voltage to that of the referencevoltage if it becomes lower than the level of the reference voltage; anda MOS diode for generating the third internal voltage of the level lowerthan that of the first internal voltage at an output terminal of thesecond internal voltage generation means when the memory device is inany other mode including the refresh mode.

In accordance with another aspect of the present invention, there isprovided an internal voltage generation circuit of a semiconductormemory device comprising: reference voltage generation means forgenerating a first reference voltage and a second reference voltage ascontrol signals for internal voltage supply, first internal voltagegeneration means for generating a first internal voltage of a desiredlevel in response to the first reference voltage from the referencevoltage generation means; reference voltage transfer means responsive toan enable signal resulting from a logical operation of an active controlsignal indicative of an active mode and a refresh control signalindicative of a refresh mode and the first and second reference voltagesfrom the reference voltage generation means, for transferring the firstreference voltage when the memory device is in the active mode and thesecond reference voltage when the memory device is in any other modeincluding the refresh mode; and second internal voltage generation meansresponsive to an output voltage from the reference voltage transfermeans for generating a second internal voltage of the same level as thatof the first internal voltage if the output voltage is the firstreference voltage and a third internal voltage of a level lower thanthat of the first internal voltage if the output voltage is the secondreference voltage.

Preferably, the first internal voltage is supplied to a row path &control logic in the memory device and the second and third internalvoltages are supplied to a column path & control logic and a data path &control logic in the memory device.

Preferably, the first internal voltage generation means includes:current mirror amplification means for comparing the first internalvoltage with the first reference voltage to obtain a differencetherebetween and amplifying the obtained difference; and pull-up meansfor raising the level of the first internal voltage to that of the firstreference voltage if it becomes lower than the level of the firstreference voltage.

Preferably, the second internal voltage generation means includes:current minor amplification means for comparing the second (or third)internal voltage with the first (or second) reference voltage to obtaina difference therebetween and amplifying the obtained difference; andpull-up means for raising the level of the second (or third) internalvoltage to that of the first (or second) reference voltage if it becomeslower than the level of the first (or second) reference voltage.

The first internal voltage generation means may include: first currentmirror amplification means for comparing the fist internal voltage withthe first reference voltage to obtain a difference therebetween andamplifying the obtained difference; and first pull-up means for raisingthe level of the first internal voltage to that of the first referencevoltage if it becomes lower than the level of the first referencevoltage; and the second internal voltage generation means may include:second current mirror amplification means for comparing the second (orthird) internal voltage with the first (or second) reference voltage toobtain a difference therebetween and amplifying the obtained difference;and second pull-up means for raising the level of the second (or third)internal voltage to that of the first (or second) reference voltage ifit becomes lower than the level of the first (or second) referencevoltage.

In accordance with a further aspect of the present invention, there isprovided an internal voltage generation circuit of a semiconductormemory device comprising: reference voltage generation means forgenerating a first reference voltage and a second reference voltage ascontrol signals for internal voltage supply, first internal voltagegeneration means for generating a first internal voltage of a desiredlevel in response to the first reference voltage from the referencevoltage generation means; internal voltage transfer means responsive toan enable signal resulting from a logical operation of an active controlsignal indicative of an active mode and a refresh control signalindicative of a refresh mode for, when the memory device is in theactive mode, receiving the first internal voltage from an outputterminal of the first internal voltage generation means and outputting asecond internal voltage of the same level as that of the first internalvoltage to an output terminal of second internal voltage generationmeans; and the second internal voltage generation means responsive tothe enable signal and the second reference voltage from the referencevoltage generation means for generating a third internal voltage of alevel lower than that of the first internal voltage when the memorydevice is in any other mode including the refresh mode.

Preferably, the first internal voltage is supplied to a row path &control logic in the memory device and the second and third internalvoltages are supplied to a column path & control logic and a data path &control logic in the memory device.

Preferably, the first internal voltage generation means includes:current mirror amplification means for comparing the first internalvoltage with the first reference voltage to obtain a differencetherebetween and amplifying the obtained difference; and pull-up meansfor raising the level of the first internal voltage to that of the firstreference voltage if it becomes lower than the level of the firstreference voltage.

Preferably, the second internal voltage generation means includes:current mirror amplification means responsive to the enable signal for,only when the memory device is in any other mode including the refreshmode, comparing the third internal voltage with the second referencevoltage to obtain a difference therebetween and amplifying the obtaineddifference; and pull-up means for raising the level of the thirdinternal voltage to that of the second reference voltage if it becomeslower than the level of the second reference voltage.

The first internal voltage generation means may include: first currentmirror amplification means for comparing the first internal voltage withthe first reference voltage to obtain a difference therebetween andamplifying the obtained difference; and first pull-up means for raisingthe level of the first internal voltage to that of the first referencevoltage if it becomes lower than the level of the first referencevoltage; and the second internal voltage generation means may include:second current mirror amplification means responsive to the enablesignal for, only when the memory device is in any other mode includingthe refresh mode, comparing the third internal voltage with the secondreference voltage to obtain a difference therebetween and amplifying theobtained difference; and second pull-up means for raising the level ofthe third internal voltage to that of the second reference voltage if itbecomes lower than the level of the second reference voltage.

In accordance with yet another aspect of the present invention, there isprovided an internal voltage generation circuit of a semiconductormemory device comprising: internal voltage generation means forsupplying a fist internal voltage of a desired level to a row path &control logic; and internal voltage transfer means for receiving thefirst internal voltage from the internal voltage generation means and,in response to an enable signal resulting from a logical operation of anactive control signal indicative of an active mode and a refresh controlsignal indicative of a refresh mode, supplying a second internal voltageof the same level as that of the first internal voltage to a column path& control logic and a data path & control logic when the memory deviceis in the active mode and a third internal voltage of a level lower thanthat of the first internal voltage to the column path & control logicand data path & control logic when the memory device is in any othermode including the refresh mode, wherein the internal voltage transfermeans includes: a MOS transistor for supplying the second internalvoltage of the same level as that of the first internal voltage inresponse to the enable signal; and a MOS diode for dropping the firstinternal voltage by a predetermined threshold voltage thereof andsupplying the resulting voltage as the third internal voltage.

Preferably, the MOS transistor is a PMOS (P-channel Metal OxideSemiconductor) transistor, which is turned on when the active controlsignal goes high in level and the refresh control signal goes low inlevel.

The MOS diode maybe an NMOS (N-channel Metal Oxide Semiconductor) diode.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and other advantages of thepresent invention will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 is a general conceptual diagram of a semiconductor memory device;

FIG. 2 is a conceptual diagram of an internal voltage generation circuitof a conventional semiconductor memory device;

FIG. 3 is a conceptual diagram of an internal voltage generation circuitof a semiconductor memory device according to the present invention;

FIG. 4A is a circuit diagram showing the configuration of a firstembodiment of the internal voltage generation circuit of thesemiconductor memory device according to the present invention;

FIG. 4B is a circuit diagram showing the configuration of a secondembodiment of the internal voltage generation circuit of thesemiconductor memory device according to the present invention;

FIG. 4C is a circuit diagram showing the configuration of a thirdembodiment of the internal voltage generation circuit of thesemiconductor memory device according to the present invention; and

FIG. 5 is a circuit diagram showing the configuration of a fourthembodiment of the internal voltage generation circuit of thesemiconductor memory device according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 is a conceptual diagram of an internal voltage generation circuitof a semiconductor memory device according to the present invention. Asshown in this drawing, the internal voltage generation circuit accordingto the present invention comprises a first Vperi generator 31 forgenerating an internal voltage Vperi_1 to a row path & control logic inresponse to an external voltage Vcc applied thereto. The internalvoltage Vperi_1 from the first Vperi generator 31 is always applied tothe row path & control logic since an operating voltage is alwaysnecessary therefor. The internal voltage generation circuit according tothe present invention further comprises a second Vperi generator 32 forgenerating an internal voltage to a column path & control logic and adata path & control logic in response to the external voltage Vccapplied thereto. The column path & control logic and the data path &control logic are selectively applied with the internal voltage from thesecond Vperi generator 32 since whether they are involved in the currentoperation mode of the memory device or not is determined according tothe operation mode.

Preferably, the second Vperi generator 32 determines the level of itsoutput voltage in response to an active control signal Active and arefresh control signal Refresh inputted thereto. That is, where thememory device is in an active mode, the second Vperi generator 32outputs an internal voltage Vperi_2 of the same level as that of theinternal voltage Vperi_1. However, in the case where the memory deviceis in a standby mode including a refresh mode in which the column path &control logic and the data path & control logic are not involved in theoperation of the memory device, the second Vperi generator 32 outputs aninternal voltage Vperi_3 of a level lower than that of the internalvoltage Vperi_1.

FIG. 4A is a circuit diagram showing the configuration of a firstembodiment of the internal voltage generation circuit of thesemiconductor memory device according to the present invention. As shownin this drawing, the internal voltage generation circuit according tothe first embodiment comprises a reference voltage generator 100 forgenerating a reference voltage Vr1 to be used as a control signal forinternal voltage supply, a first Vperi generator 110 for generating aninternal voltage Vperi_1 of a constant level in response to thereference voltage Vr1 from the reference voltage generator 100, and asecond Vperi generator 120 responsive to an enable signal resulting froma logical operation of an active control signal Active indicative of anactive mode and a refresh control signal Refresh indicative of a refreshmode and the reference voltage Vr1 from the reference voltage generator100, for generating an internal voltage Vperi_2 of the same level asthat of the internal voltage Vperi_1 when the memory device is in theactive mode and an internal voltage Vperi_3 of a level lower by apredetermined value than that of the internal voltage Vperi_1 when thememory device is in any other mode including the refresh mode.

A detailed description will hereinafter be given of the operation of theinternal voltage generation circuit with the above-stated configurationaccording to the first embodiment.

First, the reference voltage Vr1 for the internal voltage Vperi_1 isgenerated by the reference voltage generator 100 and applied to a gateof an NMOS (N-channel Metal-Oxide Semiconductor) transistor N11 of afirst current minor amplifier 111 in the first Vperi generator 110. Atthis time, since an NMOS transistor N15 is always applied with anexternal voltage Vcc at its gate, it is always kept ON, thereby allowingthe first current minor amplifier 111 to be always operated. As aresult, the internal voltage Vperi_1 of the constant level is outputtedat a gate of an NMOS transistor N12, or an output terminal of the firstVperi generator 110, according to the reference voltage Vr1. Thisinternal voltage Vperi_1 is applied as a high voltage source to a rowpath & control logic.

The first current mirror amplifier 111 is operated in the followingmanner. If the reference voltage Vr1 is applied to the gate of the NMOStransistor N11 under the condition that the NMOS transistor N15 remainsON, then the internal voltage Vperi_1 of the constant level is outputtedat the gate of the NMOS transistor N12. At this time, if the internalvoltage Vperi_1 becomes lower in level than the reference voltage Vr1, anode B becomes relatively higher in voltage level than a node A. In thiscase, because two PMOS (P-channel Metal-oxide Semiconductor) transistorsP11 and P12 are connected in common to the node B at their gates, theyincrease in resistance, thereby causing the voltage level at the node Ato become lower than the previous one. As a result, a PMOS transistorP15 becomes lower in gate voltage level, thereby causing a larger amountof current to flow from the external voltage Vcc so as to raise thelevel of the internal voltage Vperi_1. On the contrary, if the internalvoltage Vperi_1 becomes higher in level than the reference voltage Vr1,the node B becomes relatively lower in voltage level than the node A. Inthis case, the two PMOS transistors P11 and P12 decrease in resistance,so the voltage level at the node A becomes higher than the previous one.As a result, the PMOS transistor P15 becomes higher in gate voltagelevel, thereby causing a smaller amount of current to flow from theexternal voltage Vcc, which leads to a reduction in the level of theinternal voltage Vperi_1. Consequently, the internal voltage Vperi_1 ofthe constant level is generated and outputted at the output terminal ofthe first Vperi generator 110.

On the other hand, the second Vperi generator 120 includes a secondcurrent mirror amplifier 121 designed in such a manner that a PMOStransistor P17 and an NMOS transistor N16 thereof are controlled by acontrol signal from an inverter IV12. The active control signal Activegoes high in level in a read/write mode or the refresh mode to selectone word line in the memory device. The refresh control signal Refreshgoes high in level when the refresh mode is executed in response to anauto-refresh command, a self-refresh command or an external command.

As shown in FIG. 4A, an inverted version of the refresh control signalRefresh and the active control signal Active are inputted to the inputof a NAND gate ND10. The NAND gate ND10 outputs a low-level signal whenthe inputted signals are both high in level. In this regard, only whenthe memory device is in the active mode, the output of the NAND gateND10 is kept low in level. As a result, only when the memory device isin the active mode, the output of the inverter IV12 goes high in levelto turn the PMOS transistor P17 on and the NMOS transistor N16 off,thereby allowing the second current minor amplifier 121 to be normallyoperated. Consequently, in this case, the second current minor amplifier121 is operated in the same manner as the first current mirror amplifier111 to output the internal voltage Vperi_2 of the same level as that ofthe internal voltage Vperi_1 at an output terminal of the second Vperigenerator 120. This internal voltage Vperi_2 is supplied to a columnpath & control logic and a data path & control logic.

On the other hand, in the case where the memory device is in any othermode including the refresh mode, for example, a standby mode, the outputof the inverter IV12 goes low in level to turn the PMOS transistor P17on and the NMOS transistor N16 off, so the second current minoramplifier 121 is not operated However, the internal voltage Vperi_1generated by the first Vperi generator 110 is inputted to a MOS(Metal-Oxide Semiconductor) diode D10 so that the internal voltageVperi_3 can be outputted at the output terminal of the second Vperigenerator 120. Namely, the internal voltage Vperi_1 is inputted to theMOS diode D10 and then outputted as the internal voltage Vperi_3. Atthis time, the internal voltage Vperi_3 has a level lower by a thresholdvoltage Vt of the MOS diode D10 than that of the internal voltageVperi_1 inputted to the MOS diode D10. Accordingly, by adjusting thethreshold voltage Vt of the diode D10, an internal voltage Vperi_3 of adesired level can be generated and supplied to the column path & controllogic and the data path & control logic in the standby mode.

In brief, the internal voltage generation circuit according to the firstembodiment as described above always supplies an internal voltageVperi_1 of a constant level to the row path & control logic, andsupplies an internal voltage Vperi_2 of the same level as that of theinternal voltage Vperi_1 to the column path & control logic and the datapath & control logic when the memory device is in the active mode and aninternal voltage Vperi_3 of a level lower by a predetermined thresholdvoltage Vt than that of the internal voltage Vperi_1 to the column path& control logic and the data path & control logic when the memory deviceis in the standby mode including the refresh mode. Therefore, theinternal voltage generation circuit according to the first embodimentcan reduce unnecessary current leakage and power consumption of thememory device by adjusting the supply level of a specific internalvoltage according to the operation mode of the memory device.

FIG. 4B is a circuit diagram showing the configuration of a secondembodiment of the internal voltage generation circuit of thesemiconductor memory device according to the present invention. As shownin this drawing, the internal voltage generation circuit according tothe second embodiment comprises a reference voltage generator 200 forgenerating a reference voltage Vr1 and a reference voltage Vr2 to beused as control signals for internal voltage supply, a first Vperigenerator 210 for generating an internal voltage Vperi_1 of a constantlevel in response to the reference voltage Vr1 from the referencevoltage generator 200, a reference voltage transfer circuit 203responsive to an enable signal resulting from a logical operation of anactive control signal Active and a refresh control signal Refresh andthe reference Voltages Vr1 and Vr2 from the reference voltage generator200, for transferring the reference voltage Vr1 when the memory deviceis in an active mode and the reference voltage Vr2 when the memorydevice is in any other mode including a refresh mode, and a second Vperigenerator 220 responsive to an output voltage from the reference voltagetransfer circuit 203 for generating an internal voltage Vperi_2 of thesame level as that of the internal voltage Vperi_1 if the output voltageis the reference voltage Vr1 and an internal voltage Vperi_3 of a levellower by a predetermined value than that of the internal voltage Vperi_1if the output voltage is the reference voltage Vr2. Here, the activecontrol signal Active and the refresh control signal Refresh are thesame as those used in the first embodiment

A detailed description will hereinafter be given of the operation of theinternal voltage generation circuit with the above-stated configurationaccording to the second embodiment

First, the reference voltage Vr1 for the internal voltage Vperi_1 isgenerated by the reference voltage generator 200 and applied to a gateof an NMOS transistor N21 of a first current minor amplifier 211 in thefirst Vperi generator 210. Then, the first current mirror amplifier 211is operated in the same manner as the first current minor amplifier 111in the first embodiment to output the internal voltage Vperi_1 of theconstant level at an output terminal of the first Vperi generator 210according to the reference voltage Vr1. This internal voltage Vperi_1 isapplied as a high voltage source to a row path & control logic.

On the other hand, the second Vperi generator 220 includes a secondcurrent mirror amplifier 221 designed in such a manner that it iscontrolled by the active control signal Active and refresh controlsignal Refresh applied to the reference voltage transfer circuit 203, inorder to supply a specific internal voltage to a column path & controllogic and a data path & control logic. That is, since an NMOS transistorN26 is always applied with an external voltage Vcc at its gate, it isalways kept ON, thereby allowing the second current mirror amplifier 221to be always operated. However, a voltage to a gate of an NMOStransistor N23 is controlled by the active control signal Active and therefresh control signal Refresh.

In a similar manner to in the first embodiment, only when the memorydevice is in the active mode, the output of a NAND gate ND20 goes low inlevel and the output of an inverter IV22 thus goes high in level. Inthis case, a transfer gate T21 is turned on and a transfer gate T22 isturned off, thereby causing the reference voltage Vr1 to be applied tothe gate of the NMOS transistor N23. As a result, the second currentmirror amplifier 221 is operated in the same manner as the first currentmirror amplifier 211 to output the internal voltage Vperi_2 of the samelevel as that of the internal voltage Vperi_1 at an output terminal ofthe second Vperi generator 220. This internal voltage Vperi_2 issupplied to the column path & control logic and the data path & controllogic.

On the other hand, in the case where the memory device is in any othermode including the refresh mode, for example, a standby mode, the outputof the NAND gate ND20 goes high in level and the output of the inverterIV22 thus goes low in level. In this case, the transfer gate T21 isturned off and the transfer gate T22 is turned on, thereby causing thereference voltage Vr2 to be applied to the gate of the NMOS transistorN23. As a result, the second current minor amplifier 221 is operated tooutput the internal voltage Vperi_3 of the level lower by thepredetermined value than that of the internal voltage Vperi_1 at theoutput terminal of the second Vperi generator 220 according to thereference voltage Vr2. This internal, voltage Vperi_3 is supplied to thecolumn path & control logic and the data path & control logic.

In brief, similarly to the first embodiment, the internal voltagegeneration circuit according to the second embodiment as described abovecan reduce unnecessary current leakage and power consumption of thememory device by adjusting the supply level of a specific internalvoltage according to the operation mode of the memory device.

FIG. 4C is a circuit diagram showing the configuration of a thirdembodiment of the internal voltage generation circuit of thesemiconductor memory device according to the present invention. As shownin this drawing, the internal voltage generation circuit according tothe third embodiment comprises a reference voltage generator 300 forgenerating a reference voltage Vr1 and a reference voltage Vr2 to beused as control signals for internal voltage supply, a first Vperigenerator 310 for generating an internal voltage Vperi_1 of a constantlevel in response to the reference voltage Vr1 from the referencevoltage generator 300, and an internal voltage transfer circuit 330responsive to an enable signal resulting from a logical operation of anactive control signal Active and a refresh control signal Refresh for,when the memory device is in an active mode, receiving the internalvoltage Vperi_1 from an output terminal of the first Vperi generator 310and outputting an internal voltage Vperi_2 of the same level as that ofthe internal voltage Vperi_1 to an output terminal of a second Vperigenerator 320. The second Vperi generator 320 is responsive to theenable signal and the reference, voltage Vr2 from the reference voltagegenerator 300 to generate an internal voltage Vperi_3 of a level lowerby a predetermined value than that of the internal voltage Vperi_1 whenthe memory device is in any other mode including a refresh mode. Here,the active control signal Active and the refresh control signal Refreshare the same as those used in the first embodiment.

A detailed description will hereinafter be given of the operation of theinternal voltage generation circuit with the above-stated configurationaccording to the third embodiment First, the reference voltage Vr1 forthe internal voltage Vperi_1 is generated by the reference voltagegenerator 300 and applied to a gate of an NMOS transistor N31 of a firstcurrent mirror amplifier 311 in the fist Vperi generator 310. Then, thefirst current minor amplifier 311 is operated in the same manner as thefirst current minor amplifier 111 in the first embodiment to output theinternal voltage Vperi_1 of the constant level at the output terminal ofthe first Vperi generator 310 according to the reference voltage Vr1.This internal voltage Vperi_1 is applied as a high voltage source to arow path & control logic.

On the other hand, in order to supply a specific internal voltage to acolumn path & control logic and a data path & control logic, a secondcurrent mirror amplifier 321 in the second Vperi generator 320 and theinternal voltage transfer circuit 330 are controlled by the activecontrol signal Active and refresh control signal Refresh which are thesame as those in the first embodiment. Namely, only when the memorydevice is in the active mode, the output of a NAND gate ND30 goes low inlevel. In this case, a PMOS transistor P37 is turned on and an NMOStransistor N36 is turned off, so the second current minor amplifier 321is not operated. However, a transfer gate T30 of the internal voltagetransfer circuit 330 is turned on to output the internal voltage Vperi_2of the same level as that of the internal voltage Vperi_1 at the outputterminal of the second Vperi generator 320. This internal voltageVperi_2 is supplied to the column path & control logic and the data path& control logic.

On the other hand, when the memory device is in any other mode includingthe refresh mode, for example, a standby mode, the output of the NANDgate ND20 goes high in level. In this case, the transfer gate T31 isturned off, the PMOS transistor P37 is turned off and the NMOStransistor N36 is turned on, so the second current minor amplifier 321is normally operated. As a result, since the reference voltage Vr2 isapplied to a gate of an NMOS transistor N33, the second current mirroramplifier 221 is operated to output the internal voltage Vperi_3 of thelevel lower by the predetermined value than that of the internal voltageVperi_1 at the output terminal of the second Vperi generator 220according to the reference voltage Vr2. This internal voltage Vperi_3 issupplied to the column path & control logic and the data path & controllogic.

Therefore, similarly to the first and second embodiments, the internalvoltage generation circuit according to the third embodiment asdescribed above can reduce unnecessary current leakage and powerconsumption of the memory device by adjusting the supply level of aspecific internal voltage according to the operation mode of the memorydevice.

FIG. 5 is a circuit diagram showing the configuration of a fourthembodiment of the internal voltage generation circuit of thesemiconductor memory device according to the present invention. As shownin this drawing, the internal voltage generation circuit according tothe fourth embodiment comprises a Vperi generator 510 for supplying aninternal voltage Vperi_1 of a constant level to a row path & controllogic, and an internal voltage transfer circuit 520 for receiving theinternal voltage Vperi_1 from the Vperi generator 510 and, in responseto an enable signal resulting from a logical operation of an activecontrol signal Active and a refresh control signal Refresh, supplying aninternal voltage Vperi_2 of the same level as that of the internalvoltage Vperi_1 to a column path & control logic and a data path &control logic when the memory device is in an active mode and aninternal voltage Vperi_3 of a level lower by a predetermined value thanthat of the internal voltage Vperi_1 to the column path & control logicand data path & control logic when the memory device is in any othermode including a refresh mode. The internal voltage transfer circuit 520includes a PMOS transistor P50 for supplying the internal voltageVperi_2 in response to the enable signal, and a MOS diode D50 fordropping the internal voltage Vperi_1 by a predetermined thresholdvoltage Vt thereof and supplying the resulting voltage as the internalvoltage Vperi_3. Here, the active control signal Active and the refreshcontrol signal Refresh are the same as those used in the firstembodiment.

A detailed description will hereinafter be given of the operation of theinternal voltage generation circuit with the above-stated configurationaccording to the fourth embodiment. As shown in FIG. 5, in a differentmanner from the first to third embodiments, the fourth embodimentemploys only one internal voltage generator, or the Vperi generator 510.

First, the internal voltage Vperi_1 is supplied as a high voltage sourceto the row path & control logic that must be applied with a constantoperating voltage irrespective of the operation mode of the memorydevice. On the other hand, when the memory device is in the active mode,the active control signal Active goes high in level and the refreshcontrol signal Refresh goes low in level, thereby causing the output ofa NAND gate ND50 to become low in level. As a result, the PMOStransistor P50 is turned on to supply the internal voltage Vperi_2 ofthe same level as that of the internal voltage Vperi_1 to the columnpath & control logic and the data path & control logic. On the contrary,when the memory device is in any other mode including the refresh mode,for example, a standby mode, the output of the NAND gate ND50 becomeshigh in level and the PMOS transistor P50 is thus turned off. As aresult, the internal voltage Vperi_3 of the level that is lower by thethreshold voltage Vt of the MOS diode D50 than that of the internalvoltage Vperi_1 is supplied to the column path & control logic and thedata path & control logic.

Therefore, through the use of only one internal voltage generator, theinternal voltage generation circuit according to the fourth embodimentas described above can reduce unnecessary current leakage and powerconsumption of the memory device by adjusting the supply level of aspecific internal voltage according to the operation mode of the memorydevice, similarly to the first to third embodiments.

As apparent from the above description, the present invention providesan internal voltage generation circuit of a semiconductor memory devicewhich is capable of supplying voltages of different levels to a columnpath & control logic and data path & control logic in the memory deviceaccording to different operation modes of the memory device. The columnpath & control logic and data path & control logic are applied with anormal operating voltage when they are involved in the current operationmode of the memory device, whereas with a lower voltage when they arenot involved. Therefore, the present invention has the effect ofefficiently managing internal voltages of the semiconductor memorydevice and reducing current leakage of the memory device and, in turn,unnecessary power consumption thereof.

Although the preferred embodiments of the present invention have beendisclosed for illustrative purposes, those skilled in the art willappreciate tat various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims.

1. An internal voltage generation circuit of a semiconductor memorydevice comprising: reference voltage generation means for generating areference voltage as a control signal for internal voltage supply; firstinternal voltage generation means for generating a first internalvoltage of a desired level in response to said reference voltage fromsaid reference voltage generation means; and second internal voltagegeneration means responsive to an enable signal resulting from a logicaloperation of an active control signal indicative of an active mode and arefresh control signal indicative of a refresh mode and said referencevoltage from said reference voltage generation means, for generating asecond internal voltage of the same level as that of said first internalvoltage when said memory device is in said active mode and a thirdinternal voltage of a level lower than that of said first internalvoltage when said memory device is in any other mode including saidrefresh mode.
 2. The internal voltage generation circuit as set forth inclaim 1, wherein said first internal voltage is supplied to a row path &control logic in said memory device and said second and third internalvoltages are supplied to a column path & control logic and a data path &control logic in said memory device.
 3. The internal voltage generationcircuit as set forth in claim 1, wherein said first internal voltagegeneration means includes: current mirror amplification means forcomparing said first internal voltage with said reference voltage toobtain a difference therebetween and amplifying the obtained difference;and pull-up means for raising the level of said first internal voltageto that of said reference voltage if it becomes lower than the level ofsaid reference voltage.
 4. The internal voltage generation circuit asset forth in claim 1, wherein said second internal voltage generationmeans includes: current mirror amplification means responsive to saidenable signal for, only when said memory device is in said active mode,comparing said second internal voltage with said reference voltage toobtain a difference therebetween and amplifying the obtained difference;pull-up means for raising the level of said second internal voltage tothat of said reference voltage if it becomes lower than the level ofsaid reference voltage; and a MOS (Metal-Oxide Semiconductor) diode forgenerating said third internal voltage of the level lower than that ofsaid first internal voltage at an output terminal of said secondinternal voltage generation means when said memory device is in anyother mode including said refresh mode.
 5. The internal voltagegeneration circuit as set forth in claim 1, wherein: said first internalvoltage generation means includes: first current mirror amplificationmeans for comparing said first internal voltage with said referencevoltage to obtain a difference therebetween and amplifying the obtaineddifference; and first pull-up means for raising the level of said firstinternal voltage to that of said reference voltage if it becomes lowerthan the level of said reference voltage; and said second internalvoltage generation means includes: second current mirror amplificationmeans responsive to said enable signal for, only when said memory deviceis in said active mode, comparing said second internal voltage with saidreference voltage to obtain a difference therebetween and amplifying theobtained difference; second pull-up means for raising the level of saidsecond internal voltage to that of said reference voltage if it becomeslower than the level of said reference voltage; and a MOS diode forgenerating said third internal voltage of the level lower than that ofsaid first internal voltage at an output terminal of said secondinternal voltage generation means when said memory device is in anyother mode including said refresh mode.
 6. An internal voltagegeneration circuit of a semiconductor memory device comprising:reference voltage generation means for generating a first referencevoltage and a second reference voltage as control signals for internalvoltage supply, first internal voltage generation means for generating afirst internal voltage of a desired level in response to said firstreference voltage from said reference voltage generation means;reference voltage transfer means responsive to an enable signalresulting from a logical operation of an active control signalindicative of an active mode and a refresh control signal indicative ofa refresh mode and said first and second reference voltages from saidreference voltage generation means, for transferring said firstreference voltage when said memory device is in said active mode andsaid second reference voltage when said memory device is in any othermode including said refresh mode; and second internal voltage generationmeans responsive to an output voltage from said reference voltagetransfer means for generating a second internal voltage of the samelevel as that of said first internal voltage if the output voltage issaid first reference voltage and a third internal voltage of a levellower than that of said first internal voltage if the output voltage issaid second reference voltage.
 7. The internal voltage generationcircuit as set forth in claim 6, wherein said first internal voltage issupplied to a row path & control logic in said memory device and saidsecond and third internal voltages are supplied to a column path &control logic and a data path & control logic in said memory device. 8.The internal voltage generation circuit as set forth in claim 6, whereinsaid first internal voltage generation means includes: current mirroramplification means for comparing said first internal voltage with saidfirst reference voltage to obtain a difference therebetween andamplifying the obtained difference; and pull-up means for raising thelevel of said first internal voltage to that of said first referencevoltage if it becomes lower than the level of said first referencevoltage.
 9. The internal voltage generation circuit as set forth inclaim 6, wherein said second internal voltage generation means includes:current mirror amplification means for comparing said second (or third)internal voltage with said first (or second) reference voltage to obtaina difference therebetween and amplifying the obtained difference; andpull-up means for raising the level of said second (or third) internalvoltage to that of said first (or second) reference voltage if itbecomes lower than the level of said first (or second) referencevoltage.
 10. The internal voltage generation circuit as set forth inclaim 6, wherein: said first internal voltage generation means includes:first current mirror amplification means for comparing said firstinternal voltage with said first reference voltage to obtain adifference therebetween and amplifying the obtained difference; andfirst pull-up means for raising the level of said first internal voltageto that of said first reference voltage if it becomes lower than thelevel of said first reference voltage; and said second internal voltagegeneration means includes: second current mirror amplification means forcomparing said second (or third) internal voltage with said first (orsecond) reference voltage to obtain a difference therebetween andamplifying the obtained difference; and second pull-up means for raisingthe level of said second (or third) internal voltage to that of saidfirst (or second) reference voltage if it becomes lower than the levelof said first (or second) reference voltage.
 11. An internal voltagegeneration circuit of a semiconductor memory device comprising:reference voltage generation means for generating a first referencevoltage and a second reference voltage as control signals for internalvoltage supply; first internal voltage generation means for generating afirst internal voltage of a desired level in response to said firstreference voltage from said reference voltage generation means; internalvoltage transfer means responsive to an enable signal resulting from alogical operation of an active control signal indicative of an activemode and a refresh control signal indicative of a refresh mode for, whensaid memory device is in said active mode, receiving said first internalvoltage from an output terminal of said first internal voltagegeneration means and outputting a second internal voltage of the samelevel as that of said first internal voltage to an output terminal ofsecond internal voltage generation means; and said second internalvoltage generation means responsive to said enable signal and saidsecond reference voltage from said reference voltage generation meansfor generating a third internal voltage of a level lower than that ofsaid first internal voltage when said memory device is in any other modeincluding said refresh mode.
 12. The internal voltage generation circuitas set forth in claim 11, wherein said first internal voltage issupplied to a row path & control logic in said memory device and saidsecond and third internal voltages are supplied to a column path &control logic and a data path & control logic in said memory device. 13.The internal voltage generation circuit as set forth in claim 11,wherein said first internal voltage generation means includes: currentmirror amplification means for comparing said first internal voltagewith said first reference voltage to obtain a difference therebetweenand amplifying the obtained difference; and pull-up means for raisingthe level of said first internal voltage to that of said first referencevoltage if it becomes lower than the level of said first referencevoltage.
 14. The internal voltage generation circuit as set forth inclaim 11, wherein said second internal voltage generation meansincludes: current mirror amplification means responsive to said enablesignal for, only when said memory device is in any other mode includingsaid refresh mode, comparing said third internal voltage with saidsecond reference voltage to obtain a difference therebetween andamplifying the obtained difference; and pull-up means for raising thelevel of said third internal voltage to that of said second referencevoltage if it becomes lower than the level of said second referencevoltage.
 15. The internal voltage generation circuit as set forth inclaim 11, wherein: said first internal voltage generation meansincludes: first current mirror amplification means for comparing saidfirst internal voltage with said first reference voltage to obtain adifference therebetween and amplifying the obtained difference; andfirst pull-up means for raising the level of said first internal voltageto that of said first reference voltage if it becomes lower than thelevel of said first reference voltage; and said second internal voltagegeneration means includes: second current mirror amplification meansresponsive to said enable signal for, only when said memory device is inany other mode including said refresh mode, comparing said thirdinternal voltage with said second reference voltage to obtain adifference therebetween and amplifying the obtained difference; andsecond pull-up means for raising the level of said third internalvoltage to that of said second reference voltage if it becomes lowerthan the level of said second reference voltage.
 16. An internal voltagegeneration circuit of a semiconductor memory device comprising: internalvoltage generation means for supplying a first internal voltage of adesired level to a row path & control logic; and internal voltagetransfer means for receiving said first internal voltage from saidinternal voltage generation means and, in response to an enable signalresulting from a logical operation of an active control signalindicative of an active mode and a refresh control signal indicative ofa refresh mode, supplying a second internal voltage of the same level asthat of said first internal voltage to a column path & control logic anda data path & control logic when said memory device is in said activemode and a third internal voltage of a level lower than that of saidfirst internal voltage to said column path & control logic and data path& control logic when said memory device is in any other mode includingsaid refresh mode, wherein said internal voltage transfer meansincludes: a MOS transistor for supplying said second internal voltage ofthe same level as that of said first internal voltage in response tosaid enable signal; and a MOS diode for dropping said first internalvoltage by a predetermined threshold voltage thereof and supplying theresulting voltage as said third internal voltage.
 17. The internalvoltage generation circuit as set forth in claim 16, wherein said MOStransistor is a PMOS (P-channel Metal-Oxide Semiconductor) transistor,said PMOS transistor being turned on when said active control signalgoes high in level and said refresh control signal goes low in level.18. The internal voltage generation circuit as set forth in claim 16,wherein said MOS diode is an NMOS (N-channel Metal-Oxide Semiconductor)diode.